讲座题目：Variational Analysis of Non-Tree Clock Networks Considering Environmental Uncertainty
It is challenging to verify clock-skew for large-scale non-tree clock networks with environmental uncertainties such as supply voltage fluctuation and thermal temperature variations. In this talk, I will present a new variational clock-skew analysis via parameterized incremental truncated-balanced-realization method. Environmental uncertainties are firstly structurally added into the parameterized state equation of clock networks. Then a compact macromodel is obtained by the structure-preserving subspace reduction by the extended truncated-balanced realization technique. To reduce the computational cost of singular-value decomposition (SVD) during the reduction process, we propose an incremental SVD method that only needs to partially update the projection matrix by analyzing the perturbed output waveform owning to environmental uncertainties. Experiments on a number of clock networks show that compared with the macromodeling by the fast TBR method, our method reduces the computational cost in the order of 100X with a similar accuracy. In addition, compared with the macromodeling by the Krylov-subspace-based method, our method reduces the waveform error by 2X with a similar runtime.
Dr. Tan is an Associate Professor in the Department of Electrical Engineering, University of California at Riverside. He received his B.S. and M.S. degrees in electrical engineering from Fudan University, Shanghai, China in 1992 and 1995, respectively and the Ph.D. degree in electrical and computer engineering from the University of Iowa, Iowa City, in 1999.
Dr. Tan research interests include several aspects of design automation for VLSI integrated circuits – modeling and simulation of analog/RF/mixed-signal VLSI circuits, high performance power and clock distribution network simulation and design, signal integrity, power modeling, architecture-level thermal modeling and simulation, thermal optimization in nanometer VLSI design, and embedded system designs based on FPGA platforms. He has published 2 books, over 130 peer-reviewed journal and conference papers and gave over 30 invited presentations, tutorials and short courses at conferences and workshops.Dr. Tan received NSF CAREER Award in 2004, and the Outstanding Oversea Investigator Collaboration Award from the NSF of China in 2008. He received the Best Paper Award from 2007 IEEE International Conference on Computer Design (ICCD’07), a Best Paper Award Nomination from 2005 IEEE/ACM Design Automation Conference, the Best Paper Award from 1999 IEEE/ACM Design Automation Conference. He received the UC Regent’s Faculty Fellowship in 2004 and 2006 and COR (committee on Research) Research Fellowship from UCR in 2008. He also co-authored book “Symbolic Analysis and Reduction of VLSI Circuits” by Springer/Kluwer 2005 and “Advanced Model Order Reduction Techniques for VLSI Designs”, by Cambridge University Press 2007. Dr. Tan now is serving as an Associate Editor for three journals: ACM Transaction on Design Automation of Electronic Systems (TODAE), Integration, The VLSI Journal, and Journal of VLSI Design.